MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 157

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

floating-point value does so using the double-precision floating-point format. Therefore, all floating-point
numbers are stored in double-precision format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the exception of the
compare instructions (which update the CR), place the result into an FPR. Information about the status of
floating-point operations is placed into the floating-point status and control register (FPSCR) and in some
cases, after the completion of the operation’s writeback stage, into the CR. For information on how the CR
is affected by floating-point operations, see
3.7.3
The FPSCR controls the handling of floating-point exceptions and records status resulting from the
floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control bits.
FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except
for the floating-point enabled exception summary (FEX) and floating-point invalid operation exception
summary (VX). Once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0
instruction.
Table 3-4
which are control bits.
FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the
FPSCR bits directly affected by the various instructions.
Freescale Semiconductor
Reset
summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and
Floating-Point Status and Control Register (FPSCR)
MSB
0
[0], [3:12], [21:23]
Figure 3-5. Floating-Point Registers (FPRs)
[1:2], [13:20]
MPC561/MPC563 Reference Manual, Rev. 1.2
[24:31]
Bits
Table 3-4. FPSCR Bit Categories
Section 3.7.4, “Condition Register
Status, not sticky
Control
Status, sticky
Unchanged
FPR31
FPR0
FPR1
. . .
. . .
Type
(CR).”
Central Processing Unit
LSB
63
3-13