MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 147

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.2
Major features of the RCPU include:
3.3
The instruction sequencer provides centralized control over data flow between execution units and register
files. It implements the basic instruction pipeline, fetches instructions from the memory system, issues
them to available execution units, and maintains a state history that is used to back up the machine in the
event of an exception.
The instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch
queue. The BPU extracts branch instructions from the pre-fetch queue and, using branch prediction on
unresolved conditional branches, allows the instruction sequencer to fetch instructions from a predicted
target stream while a conditional branch is evaluated. The BPU folds out branch instructions for
unconditional or conditional branches unaffected by instructions in the execution stage.
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,
preserving the programming model of sequential execution. If branch prediction is incorrect, the
instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.
Freescale Semiconductor
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High-performance microprocessor
— Single clock-cycle execution for many instructions
Five independent execution units and two register files
— Independent LSU for load and store operations
— BPU featuring static branch prediction
— A 32-bit integer unit (IU)
— Fully IEEE 754-compliant FPU for both single- and double-precision operations except as
— 32 general-purpose registers (GPRs) for integer operands
— 32 floating-point registers (FPRs) for single- or double-precision operands
Facilities for enhanced system performance
— Atomic memory references
In-system testability and debugging features
High instruction and data throughput
— Condition register (CR) look-ahead operations performed by BPU
— Branch-folding capability during execution (zero-cycle branch execution time)
— Programmable static branch prediction on unresolved conditional branches
— A pre-fetch queue that can hold up to four instructions, providing look-ahead capability
— Interlocked pipelines with feed-forwarding that control data dependencies in hardware
Class code compression model support
— Efficient use of internal Flash (MPC564) and external Flash (MPC562/MPC564) by increasing
RCPU Key Features
Instruction Sequencer
noted in
code density up to 100%
Section 3.4.4, “Floating-Point Unit
MPC561/MPC563 Reference Manual, Rev. 1.2
(FPU),” or refer to the RCPU Reference Manual.
Central Processing Unit
3-3