MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1090

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
A.2.2
No address arithmetic is allowed for instruction space because the address map changes during
compression and no software tool can identify address arithmetic structures in the code. Address
arithmetic for data tables is permitted since data space is not compressed. Only instruction space is
compressed.
A.2.3
The code compression algorithm is based on creating optimal vocabularies of frequently appearing RCPU
RISC instructions or instruction halves and replacing these instructions with pointers to the vocabularies.
The system contains several sets of vocabularies for different groups of instructions. These groups are
referred to as classes.
Every instruction belongs to exactly one class. Compression of the instructions in a class may be in one of
the following modes. Refer to
A-2
•
•
•
•
•
•
•
•
1. Compression of the whole instruction into one vocabulary pointer
2. Compression of each half of the instruction into a different vocabulary
No changes in the CPU architecture
A compressor tool performs compression off-line in software using instruction class-based
algorithms optimized for the MPC56x instruction set
Decompression is done at run-time by special hardware
Optimized for cache-less systems:
— Highly effective in system solutions for a low-cache hit ratio environment and for systems with
— Deterministic program execution
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Switches between compressed and non-compressed user application sections is possible. (A
compressed subroutine can call a non-compressed one and be called from non-compressed portions
of the user application)
Adaptive vocabularies, generated for a particular application
Compressed address space is up to 1 Gbyte
Branch displacement from its target:
— Conditional branch displacement is up to 4 Kbytes
— Unconditional branch displacement is up to 4 Mbytes
fast embedded program memory
Model Limitations
Instruction Class-Based Compression Algorithm
Branch displacement is hardware limited. The compiler can enlarge the
branch scope by creating branch chains.
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
A-1.
NOTE
Freescale Semiconductor