MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1098

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
Alternatives #1 and #2 are referred to as CLASS_2a and CLASS_2b respectively.
A.2.9.4
For the MPC562/MPC564, the instruction is divided into two segments. The left segment is compressed
and mapped into a vocabulary. The vocabulary location is programmable. The right segment is either fully
bypassed by a 16-bit field or by a shorter field which is decompressed according to fixed rules.
The definition of the class includes
When the vocabulary is located in RAM #1, the class will be referred to as CLASS_3a and when the
vocabulary is located in RAM #2, the class will be referred to as CLASS_3b.
A-10
.
MSB
•
•
•
•
•
•
•
•
•
•
•
16-bit segment #1 – to be compressed
4-bit class
TP1 length=2-9
TP2 length=2-9
AS=0
For alternative #1:
— TP1 base address = base address of segment #1 vocabulary in RAM #1
— TP2 base address = base address of segment #2 vocabulary in RAM #2
— DS=0
For alternative #2:
— TP1 base address = base address of segment #2 vocabulary in RAM #1
— TP2 base address = base address of segment #1 vocabulary in RAM #2
— DS=1
TP1 length=2-9
TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there.
TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there.
DS=0
AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
Left Segment Compression and Right Segment Bypass – CLASS_3
2- to 9-bit TP1 for segment #1
Figure A-9. CLASS_3 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Compressed Instruction
16-bit segment #2 – to be bypassed
0-, 10-, 15- or 16-bit bypass for segment #2
Freescale Semiconductor