MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 345

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Burst data in progress
Cancel reservation
Kill reservation
Signal Name
Transfer start
BDIP
CR
KR
TS
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Pins
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Active
Low
Low
Low
Low
Reservation Protocol
Transfer Start
I/O
O
O
I
I
I
I
Driven by the MPC561/MPC563 when it owns the
external bus. It is part of the burst protocol. When
BDIP is asserted, the second beat in front of the
current one is requested by the master. This signal is
negated prior to the end of a burst to terminate the
burst data phase early.
Driven by an external master when it owns the
external bus. When BDIP is asserted, the second beat
in front of the current one is requested by the master.
This signal is negated prior to the end of a burst to
terminate the burst data phase early. The
MPC561/MPC563 does not support burst accesses to
internal slaves.
Driven by the MPC561/MPC563 when it owns the
external bus. Indicates the start of a transaction on the
external bus.
Driven by an external master when it owns the
external bus. It indicates the start of a transaction on
the external bus or (in show cycle mode) signals the
beginning of an internal transaction.
Each MPC500 CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX
instruction issued by the RCPU to a non-local bus on
which the
signal is used by the non-local bus interface to
back-off the cycle. Refer to
Reservation” for details.
storage reservation
Description
Section 9.5.10, “Storage
has been lost, this
External Bus Interface
9-5