MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1021

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.9.2.2
The data read message contains the data read value and the address of the target location, relative to the
previous data trace message.
The data read message has the following format:
24.9.2.3
A data trace synchronization message shall be transmitted via the auxiliary port (provided data trace is
enabled) for the following conditions:
Data trace synchronization messages provide the full address (without leading zeros) and ensure that
development tools fully synchronize with data trace regularly. Synchronization messages provide a
reference address for subsequent DTMs, in which only the unique portion of the data trace address is
transmitted.
Data trace synchronization messages are of two types:
Freescale Semiconductor
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Initial data trace message upon exit of any system reset will be a synchronization message.
Upon exit of sleep, deep-sleep and low power down mode, the first data trace message will be a
synchronization message.
Initial data trace message upon exit of background debug mode. Upon exiting BDM, the next data
trace message will be a synchronization message.
When data trace is enabled, the first data trace message will be a synchronization message.
After 255 data trace messages have been queued without synchronization, the next data trace
message will be a synchronization message.
Upon assertion of an event In (EVTI) signal. If the READI module is not disabled at reset, when
EVTI asserts, if the EC field is 0b00 in the DC register, the next data trace message will be a
synchronization message.
Upon occurrence of a watchpoint, the next data trace message will be a synchronization message.
Occurrence of queue overrun. A data trace overrun error occurs when a trace message cannot be
queued due to the queue being full (provided data trace is enabled). This causes the message queue
to be flushed, and an error message is placed as the first message in the queue. The error code
within the error message indicates that program/data/ownership trace overrun has occurred. The
next data trace message will be a synchronization message.
Data write
Data read
Data Read Message
Data Trace Synchronization Messages
TCODE (6)
[6 bits]
Figure 24-45. Data Read Message Format
MPC561/MPC563 Reference Manual, Rev. 1.2
Relative Address
Max Length = 63 bits
Min Length = 15 bits
[1 to 25 bits]
[8, 16, 24, or 32 bits]
Data Value
READI Module
24-53