MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 547

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

to the LOCK and FLIP bits of the module configuration register. This will be described in
“Switching Between Legacy and Enhanced Modes of
14.2.4
The heart of the QADC is its conversion command word (CCW) queues. This is where the module is
programmed to convert a particular channel according to a particular requirement. The queues are created
by writing CCWs into the CCW table in the register memory. The queues are controlled by the three
control registers, and their status can be read from the two status registers. As conversions are completed
the digital value is written into the result word table.
word table.
14.2.5
The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog
signals that may be converted. The externally multiplexed channels are automatically selected from the
Freescale Semiconductor
0x27E (CCW63)
0x200 (CCW0)
P = Pause Until Next Trigger
REF = Use Alternate Reference Voltage
IST = Input Sample Time
CHAN = Channel Number and End_of_Queue Code
Using the Queue and Result Word Table
External Multiplexing
BQ2
msb
NOTE 1: These offsets must be added to the module base address: A = 0x30 4800 or B = 0x30 4C00
6
P REF IST
10-bit Conversion
Conversion Command
Command Word
Word (CCW) Table
(CCW) Format
7
Begin Queue 1
End of Queue 1
Begin Queue 2
End of Queue 2
Figure 14-2. CCW Queue and Result Table Block Diagram
8
9
CHAN
MPC561/MPC563 Reference Manual, Rev. 1.2
15
lsb
Analog to Digital
Channel Select,
Sample, Hold,
Conversion
A/D Converter
and
Right Justified, Unsigned Result Format
Figure 14-2
msb
0 0
0
S
Left Justified, Unsigned Result Format
0
0
Operation.”
Left Justified, Signed Result Format
1
0 0 0
in Three Different 16-bit Formats
Result
Result
0
Software Readable
shows the CCW queue and the result
10-bit Result is
Result Word Table
7 8
7 8
7 8
Result
0 0
0 0
QADC64E Enhanced Mode Operation
0 0 0
0
0 0
lsb
15
15
15
0
0
Result 0
Result 63
Address Offsets:
0x280-0x2FF
0x300-0x37F
Section 14.3.1.3,
0x380-0x3FF
S = Sign bit
1
1
1
14-5