MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 660

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
executed again. SPE is not cleared by the QSPI. New receive data overwrites previously received data
located in the receive data segment.
Wraparound mode is properly exited in two ways:
15.6.8
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and the slave select
(PCS0/SS) input pin is pulled low by an external driver. This is possible only if the PCS0/SS pin is
configured as input by QDDR. This low input to SS is not a normal operating condition. It indicates that
a multimaster system conflict may exist, that another MCU is requesting to become the SPI network
master, or simply that the hardware is incorrectly affecting PCS0/SS. SPE in SPCR1 is cleared, disabling
the QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE in SPCR3 is asserted, the
QSPI generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing SPSR with a zero
in MODF. After correcting the mode fault problem, the QSPI can be re-enabled by asserting SPE.
The PCS0/SS pin may be configured as a general-purpose output instead of input to the QSPI. This inhibits
the mode fault checking function. In this case, MODF is not used by the QSPI.
15.7
The dual, independent, serial communication interface (DSCI) communicates with external devices
through an asynchronous serial bus. The two SCI modules are functionally equivalent, except that the
SCI1 also provides 16-deep queue capabilities for the transmit and receive operations. The SCIs are fully
compatible with other Freescale SCI systems. The DSCI has all of the capabilities of previous SCI systems
as well as several significant new features.
Figure 15-24
15-42
•
•
The CPU may disable wrap-around mode by clearing WREN. The next time end of the queue is
reached, the QSPI sets SPIF, clears SPE, and stops.
The CPU sets HALT. This second method halts the QSPI after the current transfer is completed,
allowing the CPU to negate SPE. The CPU can immediately stop the QSPI by clearing SPE;
however, this method is not recommended, as it causes the QSPI to abort a serial transfer in
process.
Serial Communication Interface
Mode Fault
is a block diagram of the SCI transmitter.
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 15-25
is a block diagram of the SCI receiver.
Freescale Semiconductor