MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 189

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.15.3
Storage control instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented
by the MPC561/MPC563.
3.15.4
The following paragraphs define the types of OEA exceptions. The exception table vector defines the
offset value by exception type. Refer to
3.15.4.1
A system reset exception occurs when:
Settings caused by reset as shown in
A non-maskable interrupt (NMI) occurs when the IRQ0 is asserted and the following registers are set.
Freescale Semiconductor
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Any reset signal is asserted: PORESET, HRESET, or SRESET
An internal reset is requested, such as from the software watchdog timer
MSR
SRR0
SRR1
FPECR
ICTRL
LCTRL1
LCTRL2
COUNTA[16:31]
COUNTB[16:31]
Storage Control Instructions
Exceptions
Register Name
System Reset Exception and NMI (0x0100)
Register
Table 3-23. Register Settings following an NMI
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-22. Settings Caused by Reset
0x0000 0000
IP depends on internal data bus configuration word; ME is unchanged.
DCMPEN is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]). All other bits are cleared
Undefined
Undefined
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
Table
10:15
Other
Bits
1:4
Table
All
3-22.
3-19.
Set to the effective address of the next instruction the
processor executes if no interrupt conditions are present
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
Setting
Description
Central Processing Unit
3-45