MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 529

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Example 3 below shows the timing for conversions in gated continuous-scan mode with the same
assumptions in the amended definition for the PF bit in this mode to reflect the condition that a gate closing
occurred before the queue completed is a proposal under consideration at this time as example 2.
Freescale Semiconductor
Trig1
(gate)
EOC
QS
Q1 RES
SSE
CF1
PF1
CWP
CWPQ1
At the end of Q1,the completion flag CF1 sets and the queue restarts. Also,
note that if the queue starts a second time and completes, the trigger overrun
flag TOR1 sets.
LAST
0
LAST
Software must set SSE
LAST
Software must clear PF1
CCW0
Figure 13-47. Gated Mode, Single-Scan Timing
8
MPC561/MPC563 Reference Manual, Rev. 1.2
CCW0
R0
CCW1
0
CCW1
R1
NOTE
CCW0
CCW0
CCW1
R0
8
CCW2
CCW1
R1
QADC64E Legacy Mode Operation
CCW3
CCW2
R2
CCW3
R3
0
13-65