MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 31

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.2.2
24.2.3
24.2.4
24.3
24.4
24.5
24.6
24.6.1
24.6.1.1
24.6.1.2
24.6.1.3
24.6.1.4
24.6.1.5
24.6.1.6
24.6.1.7
24.6.1.8
24.6.1.9
24.6.2
24.6.3
24.6.4
24.6.5
24.6.5.1
24.6.5.2
24.7
24.7.1
24.7.1.1
24.7.2
24.7.3
24.7.4
24.7.5
24.7.5.1
24.7.5.2
24.7.5.3
24.7.5.3.1
24.7.5.3.2
24.7.5.4
24.7.6
24.7.7
24.7.7.1
24.7.7.2
Freescale Semiconductor
Paragraph
Number
Parametrics .................................................................................................................... 24-4
Messages ....................................................................................................................... 24-4
Terms and Definitions .................................................................................................. 24-6
Programming Model ..................................................................................................... 24-8
Signal Interface ........................................................................................................... 24-20
Security ..................................................................................................................... 24-4
Normal ...................................................................................................................... 24-4
Disabled .................................................................................................................... 24-4
Register Map ............................................................................................................. 24-8
Accessing Memory-Mapped Locations Via
Accessing READI Tool Mapped Registers Via the Auxiliary Port ........................ 24-19
Partial Register Updates .......................................................................................... 24-19
Programming Considerations ................................................................................. 24-20
Functional Description ............................................................................................ 24-21
Functional Block Diagram ...................................................................................... 24-22
Message Priority ..................................................................................................... 24-22
Signal Protocol ........................................................................................................ 24-23
Messages ................................................................................................................. 24-24
READI Reset Configuration ................................................................................... 24-34
READI Signals ....................................................................................................... 24-36
User-Mapped Register (OTR) .............................................................................. 24-8
Tool-Mapped Registers ........................................................................................ 24-9
Device ID Register (DID) ..................................................................................... 24-9
Development Control Register (DC) .................................................................. 24-10
Mode Control Register (MC) .............................................................................. 24-11
User Base Address Register (UBA) ................................................................... 24-12
Read/Write Access Register (RWA) .................................................................. 24-13
Upload/Download Information Register (UDI) .................................................. 24-15
Data Trace Attributes 1 and 2 Registers (DTA1 and DTA2) ............................. 24-17
the Auxiliary Port ............................................................................................... 24-18
Program Trace Guidelines .................................................................................. 24-20
Compressed Code Mode Guidelines .................................................................. 24-20
Signals Implemented .......................................................................................... 24-21
Message Formats ................................................................................................ 24-28
Rules of Messages .............................................................................................. 24-31
Branch Trace Message Examples ....................................................................... 24-32
Non-Temporal Ordering of Transmitted Messages ............................................ 24-33
Reset Configuration for Debug Mode ................................................................ 24-36
Reset Configuration for Non-Debug Mode ........................................................ 24-37
Example of Indirect Branch Message ............................................................. 24-32
Example of Direct Branch Message ............................................................... 24-33
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Title
Number
Page
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