MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 171

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.9.10.3
Refer to the following sections for details on additional implementation-specific registers in the
MPC561/MPC563:
3.10
All PowerPC ISA instructions are encoded as single words (32 bits) and are consistent among all
instruction types. The fixed instruction length and consistent format simplify instruction pipelining and
permit efficient decoding to occur in parallel with operand accesses.
The PowerPC ISA instructions are divided into the following categories:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
Section 4.6, “BBC Programming
Section 6.2.2.1.2, “Internal Memory Map Register
Section 11.8, “L2U Programming
Chapter 23, “Development
Integer instructions, which include computational and logical instructions
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
Floating-point instructions, which include floating-point computational instructions, as well as
instructions that affect the floating-point status and control register (FPSCR)
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point status and control instructions
Load/store instructions., which include integer and floating-point load and store instructions
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
— Primitives used to construct atomic memory operations (lwarx and stwcx. instructions)
Flow control instructions, which include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow
— Branch and trap instructions
— Condition register logical instructions
Processor control instructions, which are used for synchronizing memory accesses.
— Move to/from SPR instructions
— Move to/from MSR
Instruction Set
Additional Implementation-Specific Registers
MPC561/MPC563 Reference Manual, Rev. 1.2
Support”
Model”
Model”
(IMMR)”
Central Processing Unit
3-27