MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 515
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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13.5.6
The on-chip periodic/interval timer can be used to generate trigger events at a programmable interval,
initiating execution of queue 1 and/or queue 2. The periodic/interval timer stays reset under the following
conditions:
The following two conditions will cause a pulsed reset of the periodic/interval timer during use:
During the low power stop mode, the periodic timer is held in reset. Since low power stop mode causes
QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer mode must be written after stop
mode is exited to release the timer from reset.
When the IMB3 internal FREEZE line is asserted and a periodic or interval timer mode is selected, the
timer counter is reset after the conversion in progress completes. When the periodic or interval timer mode
has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes
effect immediately, and the timer is held in reset. When the internal FREEZE line is negated, the timer
counter starts counting from the beginning. Refer to
IMB3
13.5.7
The QADC64E module communicates with other microcontroller modules via the IMB3. The QADC64E
bus interface unit (BIU) coordinates IMB3 activity with internal QADC64E bus activity. This section
describes the operation of the BIU, IMB3 read/write accesses to QADC64E memory locations, module
configuration, and general-purpose I/O operation.
13.5.7.1
The BIU is designed to act as a slave device on the IMB3. The BIU has the following functions:
Freescale Semiconductor
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Interface,” for more information.
Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval
timer
IMB3 system reset or the master reset is asserted
Stop mode is selected
Freeze mode is selected
A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue
2 is already using the timer
A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue
1 is not in a mode which uses the periodic/interval timer
Roll over of the timer
Respond with the appropriate bus cycle termination
Supply IMB3 interface timing to all internal module signals
Periodic / Interval Timer
Configuration and Control Using the IMB3 Interface
QADC64E Bus Interface Unit
Interval timer single-scan mode does not use the periodic/interval timer
until the single-scan enable bit is set.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Section 13.5.7, “Configuration and Control Using the
QADC64E Legacy Mode Operation
13-51
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