MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1412

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QSM Data Direction Register (QDDR) 15-13
QSM Interrupt Level Register (QILR) 15-9
QSM Pin Assignment Register (QPAR) 15-12
QSM Port Data Register (QPDR) 15-11
QSMCMMCR bit settings 15-9
QSPI 15-14
QSPI Enable (SPE) 15-42
QSPI Status Register (SPSR) 15-42
Queue 13-37
Index-12
SCI 15-42
block diagram 15-15
enable (SPE) 15-19
finished flag (SPIF) 15-22
initialization operation 15-28
loop mode (LOOPQ) 15-21
master operation flow 15-29
operating modes 15-27
operation 15-25
peripheral chip-selects 15-37
RAM 15-22
1 completion flag (CF1) 13-21
1 completion interrupt enable (CIE1) 13-16
1 operating mode (MQ1) 13-16
1 pause flag (PF1) 13-22
pin control registers 15-10
QSCI
QSPI
SCI
operation 15-51
pins 15-51
registers 15-45
master mode 15-27
slave mode 15-27
command RAM 15-23
receive RAM 15-23
transmit RAM 15-23
port QS
control register 1 (QSCI1CR) 15-59
status register 1 (QSCI1SR) 15-59
control register 0 (SPCR0) 15-17
control register 1 (SPCR1) 15-19
control register 2 (SPCR2) 15-20
control register 3 (SPCR3) 15-20
status register (SPSR) 15-20
control register 0 (SCCR0) 15-46
control register 1 (SCCR1) 15-47
data register (SCDR) 15-50
status register (SCSR) 15-48
wraparound mode 15-38
,
14-38
,
15-23
data
data register (PORTQS)
,
15-39
,
15-34
(DDRQS)
,
14-23
direction
,
,
14-22
14-17
MPC561/MPC563 Reference Manual, Rev. 1.2
15-10
,
15-42
,
,
15-42
14-17
15-11
register
queue
Queued
Queued output match TPU function (QOM) D-5
R
RAF 15-49
RAMBAR 20-4
RCW 7-11
RD/WR 9-4
RDRF 15-49
RE 15-46
RE bit 3-22
read cycle, data bus requirements, 9-31
read/write (RD/WR), 9-37
READI
real-time clock 6-19
Receive
receive buffer
1 pause interrupt enable (PIE1) 13-16
1 single-scan enable bit (SSE1) 13-16
1 trigger overrun (TOR1) 13-23
2 completion flag (CF2) 13-22
2 completion software interrupt enable (CIE2) 13-18
2 operating mode (MQ2) 13-18
2 pause flag (PF2) 13-23
2 pause software interrupt enable (PIE2) 13-18
2 single-scan enable bit (SSE2) 13-18
2 trigger overrun (TOR2) 13-24
pointers
priority 13-38
priority schemes 13-54
status (QS) 13-24
SCI 15-59
serial
compressed code mode guidelines 24-20
compression A-16
features 24-1
public messages 24-5
register map 24-8
signals 24-21
vendor-defined messages 24-5
data
error status flag (RXWARN) 16-34
RAM 15-23
time sample clock (RT) 15-53
message code 16-5
completed queue pointer (CPTQP) 15-25
end queue pointer (ENDQP) 15-25
new queue pointer (NEWQP) 15-25
peripheral interface (QSPI) 15-14
register full (RDRF) 15-49
14-19
,
15-48
,
,
3-25
,
9-37
15-57
,
,
14-39
15-57
,
14-25
,
13-63
,
14-24
,
,
Freescale Semiconductor
,
14-53
15-57
,
14-23
,
,
14-19
14-24
14-25
,
,
,
,
14-62
14-17
14-17
14-19
,
A-16
,
14-19
,