MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 192

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
when a machine check exception is taken, instruction execution resumes at offset 0x0200 from the base
address indicated by MSR[IP].
3.15.4.3
A data storage exception is never generated by the RCPU. The software may branch to this location as a
result of implementation-specific data storage protection error exception.
3.15.4.4
An instruction storage interrupt is never generated by them RCPU. The software may branch to this
location as a result of an implementation-specific instruction storage protection error exception.
3.15.4.5
The external interrupt exception is taken on assertion of the internal IRQ line to the RCPU, that is driven
by on-chip interrupt controller. The interrupt may be caused by the assertion of an external IRQ signal, by
a USIU timer, or by an internal chip peripheral. Refer to
for more information on the interrupt controller.
3-48
1
2
3
If the exception occurs due to a data error caused by a Load/Store instruction and the processor in Decompression
On mode, the SRR0 register will contain the address of the Load/Store instruction in compressed format. If the
exception occurs due to an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in MSR is
loaded from this bit when an RFI is executed.
DSISR and DAR registers are only updated when the machine check exception is caused by a data access violation.
Machine State Register (MSR)
Data Address Register (DAR)
Data/Storage Interrupt Status
Register (DSISR)
Register Name
Data Storage Exception (0x0300)
Instruction Storage Exception (0x0400)
External Interrupt (0x0500)
Table 3-25. Register Settings following a Machine Check Exception (continued)
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
Other
15:16
18:21
22:31
Bits
0:14
ME
LE
17
All
IP
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
D-form
Set to bits [21:24] of the instruction if X-form and to bits [1:4] if
D-form
Set to bits [6:15] of the instruction
Set to the effective address of the data access that caused the
interrupt
No change
Cleared to 0
Set to bits [29:30] of the instruction if X-form and to 0b00 if
Set to bit 25 of the instruction if X-form and to Bit 5 if D-form
Section 6.1.4, “Enhanced Interrupt
Description
Freescale Semiconductor
Controller,”