MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1085

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with
the CLAMP command code.
25.1.3.1
The external test (EXTEST) instruction selects the 520-bit boundary scan register. EXTEST also asserts
internal reset for the MPC561/MPC563 system logic to force a predictable beginning internal state while
performing external boundary scan operations.
By using the TAP, the register is capable of:
25.1.3.2
The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells prior to selection
of EXTEST. This initialization ensures that known data will appear on the outputs when entering the
EXTEST instruction. The SAMPLE/PRELOAD instruction also provides a means to obtain a snapshot of
system data and control signals.
25.1.3.3
The BYPASS instruction selects the single-bit bypass register as shown in
register path from TDI to the bypass register and, finally, to TDO, circumventing the 520-bit boundary
scan register. This instruction is used to enhance test efficiency when a component other than the
MPC561/MPC563 becomes the device under test.
When the bypass register is selected by the current instruction, the shift register stage is set to a logic zero
on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after
selecting the bypass register will always be a logic zero.
Freescale Semiconductor
a) scanning user-defined values into the output buffers
b) capturing values presented to input pins
c) controlling the output drive of three-state output or bidirectional pins
EXTEST
SAMPLE/PRELOAD
BYPASS
Since there is no internal synchronization between the scan chain clock
(TCK) and the system clock (CLKOUT), there must be provision of some
form of external synchronization to achieve meaningful results.
FROM TDI
SHIFT DR
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 25-5. Bypass Register
G1
1
1
Mux
NOTE
CLOCK DR
D
C
Figure
IEEE 1149.1-Compliant Interface (JTAG)
TO TDO
25-5. This creates a shift
25-31