MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 282

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.2.2.4.4
The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable, and interrupt
generation and is used for reporting the source of the interrupts. The register can be read anytime. A status
bit is cleared by writing a one to it. (Writing a zero has no effect.) More than one bit can be cleared at a time.
6.2.2.4.5
The RTCSC enables the different RTC functions and reports the source of the interrupts. The register can
be read anytime. A status bit is cleared by writing a one to it. (Writing a zero does not affect a status bit’s
value.) More than one status bit can be cleared at a time. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See
“Keep-Alive Power Registers Lock
6-42
10:11
Bits
PORESET
0:7
12
13
14
15
8
9
Field
Addr
REFBE
REFAE
TBIRQ
Name
REFB
REFA
TBF
TBE
Time Base Control and Status Register (TBSCR)
Real-Time Clock Status and Control Register (RTCSC)
—
MSB
0
1
Time base interrupt request. These bits determine the interrupt priority level of the time base.
Refer to
Reference A (TBREF0) interrupt status.
0 No match detected
1 TBREF0 value matches value in TBL
Reference B (TBREF1) interrupt status.
0 No match detected
1 TBREF1 value matches value in TBL
Reserved
Reference A (TBREF0) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFA bit is set.
Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFB bit is set.
Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is
asserted.
Time base enable
0 Time base and decrementer are disabled
1 Time base and decrementer are enabled
Figure 6-34. Time Base Control and Status Register (TBSCR)
2
Section 6.1.4, “Enhanced Interrupt
TBIRQ
3
MPC561/MPC563 Reference Manual, Rev. 1.2
4
Table 6-18. TBSCR Bit Descriptions
Mechanism.”
5
6
7
0000_0000_0000_0000
REFA REFB
8
0x2F C200
Description
Controller” for interrupt level encoding.
9
10
—
11
REFAE REFBE TBF
12
Freescale Semiconductor
13
Section 8.8.3.2,
14
TBE
LSB
15