MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 134

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2-36
HRESET
SRESET
Signal List
RSTCONF /
PORESET/
TEXP
WE[0:3]
BE[0:3]
CS[0:3]
TEA
AT[0:3]
TRST
BI
TA
STS
OE
7, 12
7, 12
7, 12
7, 11
7
7
11
11, 12
11, 12
/
7
7
7
7
/
/
1
Voltage
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
13
13
Controlled
Slew Rate
Option?
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
Development and Debug
Drive
Load
(pF)
N/A
NA
NA
2
System Control
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set.
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
Reset State
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
s
TA
TEA
OE
RSTCONF until reset
negates.
Controlled by DBGC in the
reset configuration word.
See
CS[0:3]
Controlled by bit ATWC (bit
12) of the reset configuration
word. See
PORESET/TRST
HRESET
SRESET
Function After HRESET,
Table
PORESET/TRST
6-8.
Table
Freescale Semiconductor
6-8.