MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 159

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
[15:19]
Bits
12
13
14
20
21
22
23
24
25
26
27
28
VXSQRT
VXSOFT
VXCVI
Name
VXVC
FPRF
OE
UE
FR
VE
ZE
XE
—
FI
Floating-point invalid operation exception for invalid compare.
Floating-point fraction rounded. The last floating-point instruction that
potentially rounded the intermediate result incremented the fraction.
Floating-point fraction inexact. The last floating-point instruction that
potentially rounded the intermediate result produced an inexact fraction or a
disabled exponent overflow.
Floating-point result flags. This field is based on the value placed into the
target register even if that value is undefined. Refer to
settings.
15 Floating-point result class descriptor (C). Floating-point instructions other
16-19 Floating-point condition code (FPCC). Floating-point compare
16 Floating-point less than or negative (FL or <)
17 Floating-point greater than or positive (FG or >)
18 Floating-point equal or zero (FE or =)
19 Floating-point unordered or NaN (FU or ?)
Reserved
Floating-point invalid operation exception for software request. This bit can be
altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The
purpose of VXSOFT is to allow software to cause an invalid operation
condition for a condition that is not necessarily associated with the execution
of a floating-point instruction. For example, it might be set by a program that
computes a square root if the source operand is negative.
Floating-point invalid operation exception for invalid square root. This
guarantees that software can simulate fsqrt and frsqrte, and can provide a
consistent interface to handle exceptions caused by square root operations.
Floating-point invalid operation exception for invalid integer convert.
Floating-point invalid operation exception enable.
Floating-point overflow exception enable.
Floating-point underflow exception enable. This bit should not be used to
determine whether denormalization should be performed on floating-point
stores.
Floating-point zero divide exception enable.
Floating-point inexact exception enable.
than the compare instructions may set this bit with the FPCC bits, to
indicate the class of the result.
instructions always set one of the FPCC bits to one and the other three
FPCC bits to zero. Other floating-point instructions may set the FPCC bits
with the C bit, to indicate the class of the result. Note that in this case the
high-order three bits of the FPCC retain their relational significance
indicating that the value is less than, greater than, or equal to zero.
Table 3-5. FPSCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table 3-6
for specific bit
Central Processing Unit
Not sticky
Not sticky
Not sticky
Sticky bit
Sticky bit
Sticky bit
Sticky bit
—
—
—
—
—
—
3-15