MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 294

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Reset
7-6
1
13:15
In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
Bits
10
11
12
3
4
5
6
7
8
9
DBHRS
DBSRS
GHRST
GSRST
SWRS
GPOR
OCCS
Name
CSRS
JTRS
ILBC
—
Table 7-3. Reset Status Register Bit Descriptions (continued)
Software watchdog reset status
0 No software watchdog reset has occurred
1 A software watchdog reset has occurred
Checkstop reset status
0 No enabled checkstop reset has occurred
1 An enabled checkstop reset has occurred
Debug port hard reset status
0 No debug port hard reset request has occurred
1 A debug port hard reset request has occurred
Debug port soft reset status
0 No debug port soft reset request has occurred
1 A debug port soft reset request has occurred
JTAG reset status
0 No JTAG reset has occurred
1 A JTAG reset has occurred
On-chip clock switch
0 No on-chip clock switch reset has occurred
1 An on-chip clock switch reset has occurred
Illegal bit change. This bit is set when the MPC561/MPC563 changes any of the following bits
when they are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than 20ns
0 No glitch was detected on the PORESET pin
1 A glitch was detected on the PORESET pin
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
20ns
0 No glitch was detected on the HRESET pin
1 A glitch was detected on the HRESET pin
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than 20ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and
the GSRST bit will be set.
0 No glitch was detected on SRESET pin
1 A glitch was detected on SRESET pin
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
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Description
Freescale Semiconductor