MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 767

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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17.9.3.5.2
The single output compare operation is selected by writing to only one of the two data registers (A or B),
thus enabling only one of the comparators. Following the first successful match on the enabled channel,
the output level is fixed and remains at the same level indefinitely with no further software intervention
being required. To generate a single output compare, the OCAB mode should be used to generate a flag on
both the A and the B match.
Figure 17-20
Freescale Semiconductor
Output signal
Mode selection; MODE0 = 0
Counter Bus
Internal Register, not accessible to software
16-bit
Register B1
Register B2
Register A
FLAG bit
provides an example of how the MDASM can be used to perform a single output compare.
Write to A and B
Single Output Compare Operation
In this mode, registers A and B2 are accessible to the user software (at
consecutive addresses).
0x0500
0x1000
0xxxxx
0x1100
Figure 17-19. Single Shot Output Pulse Example
MPC561/MPC563 Reference Manual, Rev. 1.2
A Event
0x1000
0xxxxx
0x1100
0x1000
0x1000
B Event
0xxxxx
0x1100
0x1100
NOTE
FLAG reset
by software
0x1000
0xxxxx
0x1100
0x0000
Reoccurrences of the timer count do not
A and B have been written again.
trigger the output pulse unless r egisters
Modular Input/Output Subsystem (MIOS14)
0x1000
0xxxxx
0x1100
0x1000
0x1000
0xxxxx
0x1100
0x1100
17-35

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