MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 911

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

22.5.2
The region base address register defines the base address of a region on the U-bus Flash memory space
that will be overlaid by a portion of the CALRAM memory space and the region size. Because eight such
regions in the Flash can be overlaid by the CALRAM, eight such registers (x = 0, 1, 2, 7) are provided.
The CRAM_RBAx[11:29] provides the base address (starting address) of the of the U-bus Flash region to
be overlaid and the CRAM_RBAx[0:3] provides size corresponding to the region. See
details. The RGN_SIZE[0] is reserved and should never be programmed to a one, because the MPC563
has only 512 Kbytes of Flash, and CRAM_RBAx[11] and CRAM_RBAx[12] should never be
programmed to a one. Also, note that if CRAM_OVLCR[CLPS] is set, each of the eight sizes are forced
Freescale Semiconductor
Bits
22
23
24
25
26
27
28
29
30
31
CALRAM Region Base Address Registers (CRAM_RBAx)
Name
S0
R1
D1
S1
R2
D2
S2
R3
D3
S3
Table 22-4. CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks
Supervisor-only/supervisor-user privilege (Space assignment) — If the data relocate (DR) bit is
set in Machine Status Register (MSR) and S0 is also set, then any access to the array block by
a user program generates an error. If DR bit is 0, both user and supervisor program can access
the array block, regardless of the value programmed in S0. The CALRAM array may be placed
in supervisor or unrestricted space.
This bit controls the highest 8-Kbyte block (lowest address) of CALRAM in the associated array.
Likewise, S1, S2, and S3 control other three blocks in the same manner. See
control bit address ranges.
S0 = 0 and DR = 0 both user and supervisor access allowed (array 8-Kbyte block)
S0 = 0 and DR = 1 both user and supervisor access allowed (array 8-Kbyte block)
S0 = 1 and DR = 0 both user and supervisor access allowed (array 8-Kbyte block)
S0 = 1 and DR = 1 only supervisor access allowed (array 8-Kbyte block)
Same as R0 except for address ranges shown on
Same as D0 except for address ranges shown on
Same as S0 except for address ranges shown on
Same as R0 except for address ranges shown on
Same as D0 except for address ranges shown on
Same as S0 except for address ranges shown on
Same as R0 except for address ranges shown on
Same as D0 except for address ranges shown on
Same as S0 except for address ranges shown on
Table 22-3. CRAMMCR Bit Descriptions (continued)
R0, D0, and S0
R1, D1, and S1
R2, D2, and S2
R3, D3, and S3
Bit Selection
MPC561/MPC563 Reference Manual, Rev. 1.2
0xXXXX 0000 – 0xXXXX 1FFF
0xXXXX 2000 – 0xXXXX 3FFF
0xXXXX 4000 – 0xXXXX 5FFF
0xXXXX 6000 – 0xXXXX 7FFF
Address Block (Relative)
Description
Table
Table
Table
Table
Table
Table
Table
Table
Table
22-4.
22-4.
22-4.
22-4.
22-4.
22-4.
22-4.
22-4.
22-4.
Table 22-4
Table 22-6
CALRAM Operation
for
for
22-15