MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1280

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
F.20
All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as minimum to the
output timing and 650 ns as a maximum. This slew rate is from 10% V
ns should be added for total 0 to V
Note: After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Note: VS_PCLK is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and
F.20.1
Note: All delays are in system clock periods.
F-64
1
MCPSM enable to VS_PCLK pulse
PWMSM output resolution
PWM output pulse
Note 1: f
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
MMCSM) submodules.
The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM
Status/Control Register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into the
counter.
Prescaler enable
MIOB VS_PCLK
MIOS Timing Characteristics
MMCSM and MPWMSM.
MPWMSM Timing Characteristics
SYS
bit (PREN)
Characteristic
Characteristic
is the internal system clock for the IMB3 bus.
f
SYS
3
Figure F-47. MCPSM Enable to VS_PCLK Pulse Timing Diagram
Table F-24. MPWMSM Timing Characteristics
Table F-23. MCPSM Timing Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
1
DD
slew rate.
SYS
Symbol
Symbol
t
t
t
CPSMC
t
PWMO
CPSMC
PWMR
ticks refer to the IMB3 internal state.
(MCPSMSCR_PSL[3:0]) -1
Min
—
2.0
1
Delay
DD
to 90% V
DD
Freescale Semiconductor
, an additional 100
2.0
Max
—
System Clock
2
Cycles
Unit