MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1351

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
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Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current outlined in
<XrefBlue>Table G.6 on page G-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in systems that
require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected. The internal
HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
DATA[0:31] (IN)
RSTCONF
HRESET
Figure G-33. Reset Timing – Configuration from Data Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
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66-MHz Electrical Characteristics
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