MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 750

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.7.3.2
17-18
SRESET
12:15
Bits
2:11
0
1
Field PREN FREN
Addr
MSB
PSL[3:0]
MCPSM Status/Control Register (MCPSMSCR)
0
Name
PREN
FREN
If the binary value 0b0001 is entered in PSL[3:0], the output signal is stuck
at zero, no clock is output.
—
1
Prescaler enable bit — This active high read/write control bit enables the MCPSM counter. The
PREN bit is cleared by reset.
0 MCPSM counter disabled.
1 MCPSM counter enabled.
Freeze bit — This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. NOTE: This line is active when
MIOS14MCR[STOP] is set or when MIOS14MCR[FREN] and the IMB3 FREEZE line are set.
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before freeze.
The FREN bit is cleared by reset.
0 MCPSM counter not frozen.
1 MCPSM counter frozen if MIOB freeze active.
Reserved
Clock prescaler — This 4-bit read/write data register stores the modulus value for loading into
the clock prescaler. The new value is loaded into the counter on the next time the counter equals
one or when disabled (PREN =0).
Figure 17-9. MCPSM Status/Control Register (MCPSMSCR)
2
Hex
0xE
0xF
0x0
0x1
0x2
0x3
3
...
Table 17-7. MCPSMSCR Bit Descriptions
PSL[3:0] Value
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-8. Clock Prescaler Setting
4
5
0b0000
0b0001
0b0010
0b0011
0b1110
0b1111
Binary
...
0000_0000_0000_0000
6
NOTE
—
0x30 6816
7
No counter clock output
Description
8
Divide Ratio
9
16
14
15
...
2
3
10
11
12
Freescale Semiconductor
13
PSL3:0
14
LSB
15