MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 636

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15-18
Bits
8:15
2:5
0
1
6
7
WOMQ
MSTR
Name
CPOL
CPHA
SPBR
BITS
Master/slave mode select
0 QSPI is a slave device and only responds to externally generated serial transfers.
1 QSPI is the system master and can initiate transmission to external SPI devices.
Wired-OR mode for QSPI pins. This bit controls the QSPI pins regardless of whether they are
used as general-purpose outputs or as QSPI outputs, and regardless of whether the QSPI is
enabled or disabled.
0 Pins designated for output by DDRQS operate in normal mode.
1 Pins designated for output by DDRQS operate in open drain mode.
Bits per transfer. In master mode, when BITSE is set in a command RAM byte, BITS determines
the number of data bits transferred. When BITSE is cleared, eight bits are transferred regardless
of the value in BITS. In slave mode, the BITS field always determines the number of bits the QSPI
will receive during each transfer before storing the received data.
Data transfers from 8 to 16 bits are supported. Illegal (reserved) values default to eight
bits.Table 15-14
Clock polarity. CPOL is used to determine the inactive state of the serial clock (SCK). It is used
with CPHA to produce a desired clock/data relationship between master and slave devices.
0 The inactive state of SCK is logic zero.
1 The inactive state of SCK is logic one.
Clock phase. CPHA determines which edge of SCK causes data to change and which edge
causes data to be captured. CPHA is used with CPOL to produce a desired clock/data
relationship between master and slave devices.
0 Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
1 Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
Serial clock baud rate. The QSPI uses a modulus counter to derive the SCK baud rate from the
MCU IMB3 clock. Baud rate is selected by writing a value from 2 to 255 into SPBR. The following
equation determines the SCK baud rate:
Refer to
Section 15.6.5.2, “Baud Rate
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-13. SPCR0 Bit Descriptions
shows the number of bits per transfer.
0001 to 0111
Bits[3:0]
Table 15-14. Bits Per Transfer
0000
1000
1001
1010
SCK Baud Rate
Reserved (defaults to 8)
Selection” for more information.
Bits per Transfer
Description
16
10
8
9
=
-------------------------- -
2
×
f
SYS
SPBR
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