MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 545

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

14.2.2
The QADC64E occupies one Kbyte, or 512 16-bit entries, of address space. Ten 16-bit registers are
control, port, and status registers, 64 16-bit entries are the CCW table, and 64 16-bit entries are the result
table, and occupy 192 16-bit address locations because the result data is readable in three data alignment
formats.
Each QADC64E module on MPC561/MPC563 has its own memory space.
map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
for QADC64E module B. Module B has the same offset scheme starting at 0x30 4C00. QADC64E_B
occupies 0x30 4C00 to 0x30 4FFF.
Freescale Semiconductor
1
0x30 4814-
0x30 4A00-
0x30 4A80-
0x30 4B00-
0x30 4AFF
0x30 4BFF
0x30 480A
0x30 480C
0x30 480E
0x30 49FF
0x30 4A7F
0x30 4B7F
0x30 4B80
0x30 4800
0x30 4802
0x30 4804
0x30 4806
0x30 4808
0x30 4810
0x30 4812
Address
Registers are accessible only as supervisor data space.
Memory Map
STOP FRZ
SIGN
EMU
CIE1
CIE2
CF1
MSB
X
0
TEST MODE
PF1 CF2
PIE
PIE
1
2
1
IRL1
SSE
SSE
1
2
2
0000 00
UNSIGNED LEFT JUSTIFIED
TRG
PF2 TOR1 TOR2
MPC561/MPC563 Reference Manual, Rev. 1.2
PORTQA
3
DDRQA
Table 14-1. QADC64E_A Address Map
SIGNED LEFT JUSTIFIED
4
CWPQ1
MQ1
MQ2
5
RESERVED
LOC
K
P
6
IRL2
FLI
RE
P
F
7
UNSIGNED RIGHT JUSTIFIED
QS
UME
SUP
RES
IST
V
8
9
Table 14-2
QCLK PRESCALER
10
PORTQB
DDRQB
Table 14-1
QADC64E Enhanced Mode Operation
11
CHAN
BQ2
CWPQ2
00 0000
00 0000
12
CWP
shows the memory map
13
shows the memory
14
LSB
15
Interrupt
Port Data
Reserved
Control 0
Control 1
Control 2
Register
Direction
Status 0
Status 1
Config.
Module
Results
Results
Results
CCWs
Test
Port
1
1
1
14-3