MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 479

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

register fields can be read or written but reserved fields read zero and writes have no effect. Typically, they
are written once when software initializes the QADC64E and are not changed afterwards.
13.3.6
Control register 1 is the mode control register for the operation of queue 1. The application software
defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. All
of the control register fields are read/write data. However, the SSE1 bit always reads as zero. Most of the
bits are typically written once when the software initializes the QADC64E, and not changed afterwards.
Freescale Semiconductor
SRESET
13:15
Bits
7:11
Field EMUX
Addr
1:2
4:6
12
0
3
Control Register 1 (QACR1)
MSB
0
0
EMUX
Name
TRG
PSH
PSA
PSL
Details of how to calculate values for PSH, PSA, and PSL, as well as
examples, are given in
Generation.”
—
—
1
00
—
Externally multiplexed mode. The EMUX bit configures the QADC64E for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] signals to
be outputs. See
0 Internally multiplexed, 16 possible channels
1 Externally multiplexed, 41 possible channels
Reserved
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] signals to queue 1 and
queue 2.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
Refer to
Reserved
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in IMB3 clocks
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64E. It serves no functional benefit in the MPC561/MPC563 and is not operational.
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in IMB3 clocks
2
Section 13.7.2, “External Trigger Input
TRG
3
0
Figure 13-9. Control Register 0 (QACR0)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-9. QACR0 Bit Descriptions
Table 13-7
0x30 480A (QACR0_A); 0x30 4C0A (QACR0_B)
4
Section 13.5.5, “QADC64E Clock (QCLK)
000
—
5
for more information.
6
NOTE
7
Description
8
Signals.”
0_0001
PSH
9
10
11
QADC64E Legacy Mode Operation
PSA
12
0
13
PSL
011
14
LSB
15
13-15