MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 86

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Overview
1.2
1-2
Figure 1-1
Debug features:
— Nexus debug port (Class 3)
— Background debug mode (BDM)
— IEEE 1194.1-compliant interface (JTAG) for boundary scan
Plastic ball grid array (PBGA) packaging
— 388 ball PBGA
— 27 mm x 27 mm body size
— 1.0 mm ball pitch
Default 40-, and optional 56-, and 66-MHz operation
-40°C–125°C
Independent power supplies
— 5-V I/O (5.0 ± 0.25 V)
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system
— 2.6 ± 0.1-V internal logic
— <150µA on-chip voltage shunt regulator for RAM standby operation
Block Diagram
is a block diagram of the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor

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