MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 6

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.7.1
3.13.7.2
3.13.8
3.13.8.1
3.13.9
3.13.9.1
3.13.9.2
3.13.10
3.13.10.1
3.13.10.2
3.13.10.3
3.13.10.4
3.13.10.5
3.13.10.6
3.13.10.7
3.13.10.8
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.14.5
3.14.6
3.15
3.15.1
3.15.1.1
3.15.1.2
3.15.2
3.15.2.1
3.15.3
3.15.4
3.15.4.1
3.15.4.2
3.15.4.3
3.15.4.4
3.15.4.5
Freescale Semiconductor
Paragraph
Number
Virtual Environment Architecture (VEA) .................................................................... 3-43
Operating Environment Architecture (OEA) ................................................................ 3-44
Classes of Instructions .............................................................................................. 3-40
Exceptions ................................................................................................................. 3-40
Branch Processor ...................................................................................................... 3-40
Instruction Fetching .................................................................................................. 3-40
Branch Instructions ................................................................................................... 3-40
Fixed-Point Processor ............................................................................................... 3-41
Floating-Point Processor ........................................................................................... 3-41
Load/Store Processor ................................................................................................ 3-42
Atomic Update Primitives ........................................................................................ 3-43
Effect of Operand Placement on Performance ......................................................... 3-43
Storage Control Instructions ..................................................................................... 3-43
Instruction Synchronize (isync) Instruction .............................................................. 3-43
Enforce In-Order Execution of I/O (eieio) Instruction ............................................. 3-44
Time Base ................................................................................................................. 3-44
Branch Processor Registers ...................................................................................... 3-44
Fixed-Point Processor ............................................................................................... 3-44
Storage Control Instructions ..................................................................................... 3-45
Exceptions ................................................................................................................. 3-45
Invalid Branch Instruction Forms ......................................................................... 3-40
Branch Prediction ................................................................................................. 3-40
Fixed-Point Instructions ........................................................................................ 3-41
General .................................................................................................................. 3-41
Optional Instructions ............................................................................................ 3-41
Fixed-Point Load with Update and Store with Update Instructions ..................... 3-42
Fixed-Point Load and Store Multiple Instructions ............................................... 3-42
Fixed-Point Load String Instructions .................................................................... 3-42
Storage Synchronization Instructions ................................................................... 3-42
Floating-Point Load and Store With Update Instructions .................................... 3-42
Floating-Point Load Single Instructions ............................................................... 3-42
Floating-Point Store Single Instructions ............................................................... 3-42
Optional Instructions ............................................................................................ 3-43
Machine State Register (MSR) ............................................................................. 3-44
Branch Processors Instructions ............................................................................. 3-44
Special Purpose Registers ..................................................................................... 3-44
System Reset Exception and NMI (0x0100) ........................................................ 3-45
Machine Check Exception (0x0200) .................................................................... 3-46
Data Storage Exception (0x0300) ......................................................................... 3-48
Instruction Storage Exception (0x0400) ............................................................... 3-48
External Interrupt (0x0500) .................................................................................. 3-48
MPC561/MPC563 Reference Manual, Rev. 1.2
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