MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 771

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

In the OPWM mode, the WOR bit selects whether the output is totem pole driven or open-drain.
17.9.4
17.9.5
When the reset signal is asserted, the MDASM registers are reset according to the values specified in
Section 17.9.6, “MDASM
17.9.6
The privilege level to access the MDASM registers depends on the MIOS14MCR[SUPV]. The privilege
level is unrestricted after reset and can be changed to supervisor by software.
17.9.6.1
The MDASM register map comprises four 16-bit register locations. As shown in below, the register block
contains four MDASM registers. Note that the MDASMSCRD is the duplication of the MDASMSCR.
This is done to allow 32-bit aligned accesses.
All unused bits return zero when read by the software. All register addresses in this section are specified
as offsets from the base address of the MDASM.
Freescale Semiconductor
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The MDASM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MDASM registers, and to control the MDASM in the different possible situations.
The MDASM is connected to four 16-bit counter buses available to that submodule instance, so
that the MDASM can select by software which one to use.
The MDASM uses the request bus to transmit the FLAG line to the interrupt request submodule
(MIRSM).
Modular I/O Bus (MIOB) Interface
Effect of RESET on MDASM
MDASM Registers
MDASM Registers Organization
The user should not write directly to the address of the MDASMSCRD. This
register’s address may be reserved for future use and should not be accessed
by the software to ensure future software compatibility.
0x30 6058
0x30 605A
Address
Registers.”
MDASM11 Data A Register (MDASMAR)
See
descriptions.
MDASM11 Data B Register (MDASMBR)
See
descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 17.9.6.2, “MDASM Data A (MDASMAR)
Section 17.9.6.3, “MDASM Data B (MDASMBR)
Table 17-18. MDASM Address Map
WARNING
MDASM11
Register
Modular Input/Output Subsystem (MIOS14)
Register” for bit
Register” for bit
17-39