MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1208

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

TPU3 ROM Functions
D.20.1.1
This 9-bit, RCPU-written parameter is used to set up the clock polarity for the SIOP data transfer. The valid
values for CHAN_CONTROL for this function are given in
written by the host before issuing the host service request (HSR) to initialize the function.
D.20.1.2
BIT_D is a RCPU-written bit that determines the direction of shift of the SIOP data. If BIT_D is zero, then
SIOP_DATA is right shifted (LSB first). If BIT_D is one then SIOP_DATA is left shifted (MSB first).
D.20.1.3
This RCPU-written parameter defines the baud rate of the SIOP function. The value contained in
HALF_PERIOD is the number of TCR1 counts for a half-SIOP clock period (for example, for a 50 baud
rate, with a TCR1 period of 240 ns, the value [(1/50)/2]/240 ns = 42) should be written to HALF_PERIOD.
The range for HALF_PERIOD is 1 to 0x8000, although the minimum value in practice will be limited by
other system conditions. See the notes in
performance of the SIOP function.
D.20.1.4
The TPU3 uses this parameter to count down the number of bits remaining during a transfer in progress.
During the SIOP initialization state, BIT_COUNT is loaded with the value contained in XFER_SIZE and
then decremented as the data is transferred. When it reaches zero, the transfer is complete and the TPU3
issues an interrupt request to the RCPU.
D.20.1.5
This RCPU-written parameter determines the number of bits that make up a data transfer. During
initialization, XFER_SIZE is copied into BIT_COUNT. XFER_SIZE is shown as a 5-bit parameter to
match the maximum size of 16 bits in SIOP_DATA, although the TPU3 uses the whole word location. For
normal use, XFER_SIZE should be in the 1- to 16-bit range.
D-56
1
Other values of CHAN_CONTROL may result in indeterminate operation.
CHAN_CONTROL
BIT_D
HALF_PERIOD
BIT_COUNT
XFER_SIZE
CHAN_CONTROL
8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 0 1
0 1 0 0 0 1 1 1 0
Table D-3. SIOP Function Valid CHAN_Control Options
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure D-32. SIOP Parameters
Section D.20.1.6,
CONTROL BITS
Data valid on clock Falling edge.
Data valid on clock Rising edge.
“SIOP_DATA” for information on the use and
Table
Resulting Action
D-3. CHAN_CONTROL must be
See
PRAM Address Offset Map.
Table 19-24
Freescale Semiconductor
for the