MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 67

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
14-1
14-2
14-3
14-4
14-5
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14-20
Freescale Semiconductor
Table
Number
QADCINT Bit Descriptions ................................................................................................. 13-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 13-14
QACR0 Bit Descriptions ...................................................................................................... 13-15
QACR1 Bit Descriptions ...................................................................................................... 13-16
Queue 1 Operating Modes .................................................................................................... 13-16
QACR2 Bit Descriptions ...................................................................................................... 13-18
Queue 2 Operating Modes .................................................................................................... 13-19
QASR0 Bit Descriptions....................................................................................................... 13-21
Pause Response..................................................................................................................... 13-25
Queue Status ......................................................................................................................... 13-25
QASR1 Bit Descriptions....................................................................................................... 13-27
CCW Bit Descriptions .......................................................................................................... 13-30
Non-Multiplexed Channel Assignments and Signal Designations....................................... 13-31
Multiplexed Channel Assignments and Signal Designations ............................................... 13-32
QADC64E Clock Programmability ...................................................................................... 13-50
Trigger Events....................................................................................................................... 13-54
Status Bits ............................................................................................................................. 13-55
Error Resulting from Input Leakage (IOFF)......................................................................... 13-76
QADC64E_A Address Map ................................................................................................... 14-3
QADC64E_B Address Map.................................................................................................... 14-4
Multiplexed Analog Input Channels....................................................................................... 14-6
Analog Input Channels ........................................................................................................... 14-7
QADCMCR Bit Descriptions ................................................................................................. 14-8
QADC64E Bus Error Response............................................................................................ 14-11
QADCINT Bit Descriptions ................................................................................................. 14-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 14-13
QACR0 Bit Descriptions ...................................................................................................... 14-15
Prescaler f
QACR1 Bit Descriptions ...................................................................................................... 14-17
Queue 1 Operating Modes .................................................................................................... 14-17
QACR2 Bit Descriptions ...................................................................................................... 14-19
Queue 2 Operating Modes .................................................................................................... 14-20
QASR0 Bit Descriptions....................................................................................................... 14-22
Pause Response..................................................................................................................... 14-26
Queue Status ......................................................................................................................... 14-26
QASR1 Bit Descriptions....................................................................................................... 14-28
CCW Bit Descriptions .......................................................................................................... 14-31
QADC64E_A Multiplexed Channel Assignments and Signal Designations ....................... 14-32
External Circuit Settling Time to 1/2 LSB (10-Bit Conversions) ....................................... 13-75
SYSCLK
Divide-by Values.................................................................................... 14-15
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
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Number
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