MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1050

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
24.14.3 Throughput
The tool can send a DSDI data message into device upon the receipt of a DSDO data message as soon as
the tool decodes the first two status bits of the DSDO data message just received and confirms valid data
from the RCPU.
An example throughput analysis is performed with the following assumptions:
The DSDI data message is 41 bits (six bits of TCODE and 35 bits of DSDI data.). It takes 41 clocks (41
bits / 1 MDI signals) to shift in the DSDI data message. It is estimated that READI will take approximately
10 clocks to decode the DSDI data message. After the message has been decoded, READI will take 35
clocks to serially shift in the 35 bits of DSDI data to the RCPU development port. Hence, it takes a total
of 86 clocks (41 + 10 + 35) to decode and shift in DSDI data from the tool to the RCPU development port.
At 28 MHz, it translates to 3079 ns (35.8 x 81) to decode and shift in DSDI data to RCPU development port
As DSDI bits are shifted into the RCPU development register, DSDO bits are shifted out from the same
RCPU development register (DPDR) and these are captured by READI.
It is estimated that READI will take approximately 10 clocks to encode the DSDO data. The DSDO
message is 41 bits (6 bits of TCODE and 35 bits of DSDO data). It will take 21 clocks (41 bits / 2 MDO
signals) for READI to transmit this message. Hence, it will take a total of 31 clocks (10 + 21) to encode
the DSDO data message and shift out the DSDO data message to the tool.
At 56 MHz, it will take 552 ns (17.8 x 31) to encode and shift out DSDO data to the tool.
Thus, it will take 3631 ns (3079 + 552) for one complete DSDI data and DSDO data messaging cycle.
24.14.4 Development Access Timing Diagrams
Figure 24-84
out-of-system reset through READI.
24-82
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READI configuration of RCPU development access and debug mode is already entered through
READI
The module is configured for reduced port mode
MCKI running at 28 MHz
MCKO running at 56 MHz
56-MHz internal operation
READI auxiliary input and output signals are free (not in middle of transmission)
No delay from tool in responding — tool keeps up with READI port
Tool reads the complete DSDO data message before shifting in DSDI data message
10 clocks estimated to format and encode/decode DSDI data and DSDO data messages within
READI
shows the timing diagram of RCPU development access and entering debug mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor