MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 703
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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the system clock and the CAN bit segments. Refer to
information on the bit timing registers.
A bit is divided into four separate non-overlapping time segments called SYNC_SEG, PROPSEG, PSEG1,
and PSEG2. These are illustrated in
the segment durations:
The sample point indicated in
bit is selected (CANCTRL1[SAMP] bit = 0). If three samples per bit are selected, the sample point
indicated in
Freescale Semiconductor
t
SYSTEM
CLOCK
S-CLOCK
TIME
QUANTUM
Transmit
point
NBT
System Clock
SS
Frequency
Figure 16-5
= t
(MHz)
56
40
25
20
16
56
40
25
20
SYNC_SEG
Table 16-8. Example System Clock, CAN Bit Rate, and S-Clock Frequencies
SYNC_SEG
Figure 16-5. Relationship between System Clock and CAN Bit Segments
SS
CAN Bit Rate
+ t
marks the position of the final sample.
(MHz)
0.500
0.500
0.500
0.500
PROPSEG
1
1
1
1
1
Figure 16-5
PROPSEG
MPC561/MPC563 Reference Manual, Rev. 1.2
Baud Rate Prescaler (PRESDIV)
+ t
Figure
Possible S-Clock
Frequency (MHz)
PSEG1
Nominal bit time (NBT)
is the position of the actual sample point if a single sample per
16-5. The period of the nominal bit time (NBT) is the sum of
1, 2, 2.5
10, 20
+ t
8, 16
56
40
25
56
40
25
PSEG2
PSEG1
Section 16.7, “Programming
Sample point
Possible Number of
Time Quanta/Bit
10, 20
2, 4, 5
8, 16
118
56
40
25
80
50
PSEG2
PRESDIV Value + 1
CAN 2.0B Controller Module
Model,” for more
20, 10, 8
2, 1
2, 1
1
1
1
1
1
1
16-9
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