MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 410

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Memory Controller
10.3.1
Figure 10-7
this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines
are connected to the respective WE in the memory device where each WE/BE line corresponds to a
different data byte.
In
transaction are supplied by the OE and the WE/BE lines (if programmed as WE/BE). When the ACS bits
in the corresponding ORx register = 00, CS is asserted at the same time that the address lines are valid.
10-12
Figure
10-8, the CSx timing is the same as that of the address lines output. The strobes for the
Memory Devices Interface Example
describes the basic connection between the MPC561/MPC563 and a static memory device. In
If CSNT is set, the WE signal is negated a quarter of a clock earlier than
normal.
MPC5xx
Figure 10-7. GPCM–Memory Devices Interface
Address
WE/BE
MPC561/MPC563 Reference Manual, Rev. 1.2
Data
CSx
OE
NOTE
Address
CE
OE
WE
Data
Memory
Freescale Semiconductor