MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 319

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Table 8-6
8.7.2
Table 8-5
8.7.3
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt
generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not
change the PLPRCR[CSRC] bit.
Freescale Semiconductor
Normal-low (“gear”)
Operation Mode
summarizes the control bit settings for the different clock power modes.
describes the clock frequency and chip functionality for each power mode.
SRAM Standby
Normal-high
Power-down
Deep-sleep
Power Mode Descriptions
Exiting from Low-Power Modes
Doze-high
Doze-low
Sleep
Not active
Not active
Not active
Active
Active
Active
Active
Active
SPLL
Normal-low (“gear”)
Table 8-4. Power Mode Control Bit Settings
Power Mode
Normal-high
Power-down
Deep-sleep
MPC561/MPC563 Reference Manual, Rev. 1.2
Doze-high
Doze-low
Table 8-5. Power Mode Descriptions
Sleep
Full frequency ÷
Full frequency ÷
Full frequency ÷
Full frequency ÷
Not active
Not active
Not active
Not active
2
2
Clocks
2
2
DFNL+1
DFNL+1
DFNH
DFNH
LPM[0:1]
00
00
01
01
10
11
11
Full functions not in use
Enabled: RTC, PIT, TB
(RCPU, BBC, FPU)
Enabled: RTC, PIT,
Disabled: extended
CSRC
Functionality
TB and DEC,
SRAM data
are shut off
1
X
X
X
0
0
1
and DEC
controller
retention
core
TEXPS
X
X
X
X
X
1
0
VDD, QVDDL, NVDDL,
VDD, QVDDL, NVDDL,
Power Pins that Need
KAPWR, IRAMSTBY
KAPWR, IRAMSTBY
KAPWR, VDDSYN,
KAPWR, VDDSYN,
KAPWR, VDDSYN,
to be Powered-Up
IRAMSTBY
IRAMSTBY
IRAMSTBY
IRAMSTBY
Clocks and Power Control
All On
All On
8-17