MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 250

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
The decrementer interrupt request is not a part of the interrupt controller. Each one of the external pins
IRQ[1:7] has its own dedicated assigned priority level. IRQ0 is also mapped, but it should be used only as
a status bit indicating that IRQ0 was asserted and generated NMI interrupt. There are eight additional
interrupt priority levels. Each one of the SIU internal interrupt sources, or any of the peripheral module
interrupt sources can be assigned by software to any one of the eight interrupt priority levels. Thus, a very
flexible interrupt scheme is implemented. The interrupt request signal generated by the interrupt controller
is driven to the RPCU core and to the IRQOUT pin (optionally). This pin may be used in peripheral mode,
when the RCPU is disabled, and the internal modules are accessed externally. The IMB interrupts are
controlled by the UIMB. The IMB provides 32 interrupt levels, and any interrupt source could be
configured to any IMB interrupt level. The UIMB contains a 32-bit register that holds the IMB interrupt
requests, and maps them to the USIU eight interrupt levels.
The interrupt controller may be programmed to operate in two modes—a regular mode or an enhanced
mode.
6.1.4.3
In regular operation mode (default setting) the interrupt controller receives interrupt requests from internal
sources, such as timers, PLL lock detector, IMB modules and from external pins IRQ[0:7]. All the internal
interrupt sources may be programmed to drive one or more of eight U-bus interrupt level lines while the
RCPU, upon receiving an interrupt request, has to read the USIU and UIMB status register in order to
determine the interrupt source.
The SIVEC register contains an 8-bit code representing the unmasked interrupt request which has the
highest priority level. The priority between all interrupt sources for the regular interrupt controller
operation is shown in
6-10
Number
0
1
2
3
4
5
6
7
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible
Mode)
If one interrupt level was configured to more than one interrupt source, the
software should read the UIPEND register in the UIMB module, and the
particular status bits in order to identify which interrupt was asserted.
Table
Priority
Highest
Level
Table 6-3. Priority of Interrupt Sources—Regular Operation
—
—
—
—
—
—
—
6-3.
MPC561/MPC563 Reference Manual, Rev. 1.2
Interrupt Source
Description
EXT_IRQ0
EXT_IRQ1
EXT_IRQ2
EXT_IRQ3
Level 0
Level 1
Level 2
Level 3
NOTE
Offset in Branch
Table (Hex)
0x0000
0x0008
0x0010
0x0018
0x0020
0x0028
0x0030
0x0038
SIVEC Interrupt Code
Freescale Semiconductor
00000000
00000100
00001000
00001100
00010000
00010100
00011000
00011100
1