MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 279

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.2.2.3.3
The transfer error status register contains a bit for each exception source generated by a transfer error. A
bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were
cleared by reset or by the normal software status bit-clearing mechanism.
Freescale Semiconductor
Reset
Reset
Reset
Bits
0:15
Bits
0:17
Field
Addr
Field
Field
Addr
18
19
MSB
MSB
16
0
0
SWSR
Name
Name
IBMT
IEXT
Transfer Error Status Register (TESR)
These bits may be set due to canceled speculative accesses which do not
cause an interrupt. The register has two identical sets of bit fields; one is
associated with instruction transfers and the other with data transfers.
—
—
17
1
1
SWT servicing sequence is written to this register. To prevent SWT time-out, a 0x556C followed
by 0xAA39 should be written to this register. The SWSR can be written at any time but returns
all zeros when read.
IEXT IBMT
Reserved
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
18
2
2
Figure 6-28. Transfer Error Status Register (TESR)
Figure 6-27. Software Service Register (SWSR)
19
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
20
Table 6-16. SWSR Bit Descriptions
4
4
Table 6-17. TESR Bit Descriptions
21
5
5
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
22
6
6
NOTE
—
0x2F C00E
0x2F C020
23
7
7
SWSR
—
Description
Description
24
8
8
25
9
9
DEXT DBM
10
10
26
11
System Configuration and Protection
11
27
12
12
28
13
13
29
—
14
14
30
LSB
15
LSB
15
31
6-39