MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 955

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.6.2
Note: These registers are unaffected by reset.
23.6.3
The ECR indicates the cause of entry into debug mode. All bits are set by the hardware and cleared when
the register is read when debug mode is disabled, or if the processor is in debug mode. Attempts to write
to this register are ignored. When the hardware sets a bit in this register, debug mode is entered only if
debug mode is enabled and the corresponding mask bit in the DER is set.
All bits are cleared to zero following reset.
Freescale Semiconductor
Reset
Reset
MSR[PR]
0:31
Bits
Field
Field
Addr
0
0
0
1
Comparator A–D Value Registers (CMPA–CMPD)
Exception Cause Register (ECR)
MSB
16
0
Mnemonic
Debug Mode
17
Table 23-16. Development Support Registers Write Access Protection
1
CMPA-D
Enable
Figure 23-15. Comparator A–D Value Register (CMPA–CMPD)
X
0
1
1
18
2
19
3
Table 23-17. CMPA-CMPD Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
In Debug Mode
Address bits to be compared
20
4
X
X
0
1
21
5
Write is performed.
Write to ECR is ignored.
Writing to DPDR is ignored.
Write is not performed.
Writing to DPDR is ignored.
Write is performed.
Write to ECR is ignored.
Write is not performed.
Program exception is generated.
22
6
SPR144–SPR147
Unaffected
Unaffected
23
CMPA-D
CMPAD
7
24
8
Description
25
9
10
26
Result
11
27
12
28
13
29
Development Support
14
30
LSB
15
31
23-41