MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 266

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6-26
1
13:14
17:18
20:21
22:23
29:31
WE/BE is selected per memory region by WEBS in the appropriate BR register in the memory controller.
Bits
15
16
19
24
25
26
27
28
LPMASK_EN Low priority request masking enable.
BURST_EN Burst enable.
NOSHOW
EICEN
MLRC
MTSC
Name
RCTX
GPC
DLK
SC
—
—
—
This bit configures the pins as shown in
Debug register lock
0 Normal operation
1 SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
Reserved
Single-chip select. This field configures the functionality of the address and data buses.
Changing the SC field while external accesses are performed is not supported. Refer to
Table
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as
RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal
that supports the low-power modes.
0 RSTCONF/TEXP functions as RSTCONF
1 RSTCONF/TEXP functions as TEXP
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to
Reserved
Memory transfer start control.
0 IRQ2/CR/SGPIOC2/MTS functions according to the MLRC bits setting
1 IRQ2/CR/SGPIOC2/MTS functions as MTS
Instruction show cycles disabled. If the NOSHOW bit is set (1), then all instruction show cycles
are NOT transmitted to the external bus.
Enhanced interrupt controller enable. See
Operation,” for more information.
0 Enhanced interrupt controller operates in regular mode (compatible with MPC555/MPC556)
1 Enhanced interrupt controller is enabled
0 Lower priority interrupt request masking is disabled
1 Lower priority interrupt request masking is enabled
0 Burst operation is enabled by the BBCMCR[BE]. Maximum burst length is fixed at 4 beats.
1 USIU initiated burst accesses on the external bus. Maximim burst length can be 4 or 8 beats
Note: Do not assert TEA on the external bus for instruction fetch while
Reserved
asserted.
and this may be programmed per memory region. Refer to
for more information.
6-10.
Table 6-7. SIUMCR Bit Descriptions (continued)
SIUMCR[BURST_EN] = 1. Do not place code at the last 8 words of a memory controller
region while SIUMCR[BURST_EN] = 1.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
6-11.
Table 6-9
Description
Section 6.1.4.4, “Enhanced Interrupt Controller
.
Section 10.2.5, “Burst
Freescale Semiconductor
Support,”