MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 883

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

21.3.3.1
An internal address comparator is used to determine if addressed information is stored in a read page
buffer. If the address of a read access matches data contained in a read page buffer, that addressed data is
transferred from the read page buffer to the data bus. An off-page read access to transfer data from the
Flash array to the data bus is not performed in this case.
21.3.4
The normal array is accessed when the SIE register bit in the UC3FMCR = 0. When SIE = 1, reads to the
array access the shadow information row.
21.3.5
The only valid writes to the UC3F array are program or erase interlock writes. In the case of program
interlock writes, the address of the write determines the location to be programmed while the data written
is transferred to the program data latches to be programmed into the array. Address and data written during
an erase interlock write is a “don’t care” and is not stored anywhere.
21.3.6
There are two fundamental high voltage operations, program and erase. Program changes a UC3F array
bitcell from a logic 1 state to a logic 0 state and is a selective operation performed on up to 32 bits at a
time. Erase changes a UC3F array bitcell from a logic 0 state to a logic 1 state and is a bulk operation
performed on one block or multiple blocks of the UC3F array.
21.3.6.1
The embedded hardware program/erase algorithm relies on an internal state machine to perform the
program and erase sequences. The embedded hardware algorithm uses an internal oscillator to control the
high voltage pulse duration and hardware control logic. The embedded hardware algorithm is also
responsible for performing all margin reads and applying high voltage pulses to ensure each bit is
programmed or erased with sufficient margin. Upon successful program or erase operation, the
program/erase hardware control logic terminates the program or erase operation with a pass status
(PEGOOD = 1). The program/erase control logic will time out in the event that the maximum program or
erase time is exceeded and return a fail status (PEGOOD = 0).
21.3.7
To modify the charge stored in an isolated element of the UC3F bit from a logic 1 state to a logic 0 state,
a programming operation is required. This programming operation applies the required voltages to change
the charge state of the selected bits without changing the logic state of any other bits in the UC3F array.
The program operation cannot change the logic 0 state to a logic 1 state; this transition must be done by
the erase operation. Programming uses a program data latch to store the data to be programmed and an
address latch to store the word address to be programmed. The UC3F Array may be programmed by byte
(8 bits), half-word (16 bits), or word (32 bits).
Freescale Semiconductor
Shadow Row Select Read Operation
Array Program/Erase Interlock Write Operation
High Voltage Operations
Programming
Array On-Page Read Operation
Overview of Program/Erase Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
CDR3 Flash (UC3F) EEPROM
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