MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 477

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

13.3.3
QADC64E ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB) in
each QADC64E.
Port A signals are referred to as PQA[7:0] when used as 8-bit general-purpose digital input or output
signals. It is configured as a digital input or digital output using the data direction register, DDRQA. When
Port A is configured as an input, a read of the PORTQA register returns the actual PQA[7:0] signal values.
When Port A is configured as an output, the contents of port register PQA are driven on the port A signals.
Port A can also be used as analog inputs AN[59:52] and external multiplexer address outputs MA[2:0].
Port B signals are referred to as PQB[7:0] when used as 8-bit general-purpose digital input-only signals.
Digital input signal states are read from the 8-bit PORTQB register. Port B can also be used as
non-multiplexed analog inputs AN[51:48] and AN[3:0], and external multiplexer analog inputs, ANw,
ANx, ANy, ANz.
During a port data register read, the actual value of the signal is reported when its corresponding bit in the
data direction register defines the signal to be an input. When the data direction bit specifies the signal to
be an output, the content of the port data register is read. PORTQA and PORTQB are not initialized by
reset.
Freescale Semiconductor
ANALOG CHANNEL:
SRESET
MULTIPLEXED ADDRESS OUTPUTS:
Field
Addr
ILBS [1:0]
IMB3 CLOCK
IMB3 IRQ [7:0]
Port Data Register (PORTQA and PORTQB)
PQA
AN5
MSB
7
9
0
PQA
AN5
(PORTQA) 0x30 4806 ; 0x30 4C06
6
8
1
Figure 13-7. Port x Data Register (PORTQA and PORTQB)
PQA
AN5
5
7
2
Figure 13-6. Interrupt Levels on IRQ with ILBS
PQA
AN5
Unaffected
00
6
3
4
MPC561/MPC563 Reference Manual, Rev. 1.2
PQA
AN5
3
5
4
01
IRQ
7:0
PQA
AN5
MA2 MA1 MA0
2
4
5
10
IRQ
PQA
AN5
15:8
1
3
6
PQA
AN5
0
2
23:16
7
11
IRQ
PQB
AN5
7
1
8
31:24
00
IRQ
PQB
AN5
9
6
0
(PORTQB) 0x30 4807, 0x30 4C07
01
IRQ
PQB
AN4
7:0
10
5
9
PQB
AN4
Unaffected
10
11
4
8
QADC64E Legacy Mode Operation
PQB
AN3
12
3
11
PQB
AN2 AN1
13
2
PQB
14
1
PQB
AN0
LSB
15
0
13-13