MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 204

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
For data breakpoint exceptions, the register shown in
Execution resumes at offset from the base address indicated by MSR[IP] as follows:
3.15.5
In general, the architecture permits instructions to be partially executed when an alignment or data storage
interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is
3-60
•
•
•
•
1
0x01C00 – For data breakpoint match
0x01D00 – For instruction breakpoint match
0x01E00 – For development port maskable request or a peripheral breakpoint
0x01F00 – For development port non-maskable request
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain
the instruction address in compressed format.
Machine State Register (MSR)
Partially Executed Instructions
Register Name
Register Name
BAR
Table 3-37. Register Settings Following a Debug Exception
Table 3-38. Register Settings for Data Breakpoint Match
MPC561/MPC563 Reference Manual, Rev. 1.2
1
DCMPE
10:15
Other
Other
Bits
Bits
ME
1:4
LE
All
IP
N
Set to the effective address of the data access as computed by
the instruction that caused the interrupt
For I-breakpoints, set to the effective address of the instruction
that caused the interrupt. For L-breakpoint, set to the effective
address of the instruction following the instruction that caused
the interrupt. For development port maskable request or a
peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port
request is asserted at reset, the value of SRR0 is undefined.
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[
If the development port request is asserted at reset, the value
of SRR1 is undefined.
No change
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Table 3-38
is set.
Description
Description
RI]
.
Freescale Semiconductor