MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 78

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

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provide maximum system safeguards against hardware and software faults. This chapter provides
a detailed explanation of this functionality.
Chapter 7,
and status.
Chapter 8, “Clocks and Power
the MPC561/MPC563.
Chapter 9, “External Bus
bus.
Chapter 10, “Memory
external memory and peripheral devices.
Chapter 11, “L-Bus to U-Bus Interface
(L-bus) and the unified bus (U-bus). The L2U module includes the Data Memory Protection Unit
(DMPU), which provides protection for data memory accesses.
Chapter 12, “U-Bus to IMB3 Bus Interface
structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3).
It controls bus communication between the U-bus and the IMB3.
Chapter 13, “QADC64E Legacy Mode
(QADC) modules on MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (MPC555
compatible) and enhanced mode. This chapter describes how the modules operate in legacy mode,
which is the default mode of operation.
Chapter 14, “QADC64E Enhanced Mode
(QADC) modules on the MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (for
MPC555 compatibility) and enhanced mode. This chapter describes how the module operates in
enhanced mode.
Chapter 15, “Queued Serial Multi-Channel
serial multi-channel module (QSMCM) which provides three serial communication interfaces: the
queued serial peripheral interface (QSPI) and two serial communications interfaces (SCI/UART).
This chapter describes the functionality of each.
Chapter 16, “CAN 2.0B Controller
(TouCAN) implemented on the MPC561/MPC563. Each TouCAN is a communication controller
that implements the Controller Area Network (CAN) protocol, an asynchronous communications
protocol used in automotive and industrial control systems. It is a high speed (one Mbit/sec), short
distance, priority based protocol that can run over a variety of mediums.
Chapter 17, “Modular Input/Output Subsystem
consists of a library of flexible I/O and timer functions including I/O port, counters, input capture,
output compare, pulse and period measurement, and PWM. Because the MIOS14 is composed of
submodules, it is easily configurable for different kinds of applications.
Chapter 18, “Peripheral Pin Multiplexing (PPM)
parallel-to-serial communications module that reduces the number of signals required to connect
“Reset.” This section describes the MPC561/MPC563 reset sources, operation, control,
Controller,” generates interface signals to support a glueless interface to
MPC561/MPC563 Reference Manual, Rev. 1.2
Interface,” describes the functionality of the MPC561/MPC563 external
Control,” describes the main timing and power control reference for
Module,” describes the three CAN 2.0B controller modules
(L2U),” describes the interface between the load/store bus
Operation.” The two queued analog-to-digital converter
Operation.” The two queued analog-to-digital converter
Module.” The MPC561/MPC563 contains one queued
(UIMB).” The U-bus to IMB3 bus interface (UIMB)
(MIOS14).” The modular I/O system (MIOS)
Module.” The PPM functions as a
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