MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 65

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

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6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
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6-26
7-1
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
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8-7
8-8
8-9
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8-13
9-1
9-2
9-3
9-4
9-5
Freescale Semiconductor
Table
Number
Multi-Level Reservation Control Pin Configuration .............................................................. 6-28
SIU Interrupt Controller – Bit Acronym Definitions.............................................................. 6-31
Data Direction Control............................................................................................................ 6-48
Reset Action Taken for Each Reset Cause ............................................................................... 7-4
Reset Configuration Word and Data Corruption/Coherency.................................................... 7-4
Reset Status Register Bit Descriptions ..................................................................................... 7-5
Reset Configuration Options .................................................................................................... 7-7
RCW Bit Descriptions ............................................................................................................ 7-11
Reset Clocks Source Configuration .......................................................................................... 8-9
TMBCLK Divisions ............................................................................................................... 8-10
Status of Clock Source............................................................................................................ 8-16
Power Supplies ....................................................................................................................... 8-21
KAPWR Registers and Key Registers.................................................................................... 8-26
SCCR Bit Descriptions ........................................................................................................... 8-30
COM and CQDS Bits Functionality ....................................................................................... 8-33
MPC561/MPC563 BIU Signals................................................................................................ 9-4
Data Bus Requirements For Read Cycles............................................................................... 9-31
Data Bus Contents for Write Cycles....................................................................................... 9-32
Priority Between Internal and External Masters over External Bus ....................................... 9-36
4 Word Burst Length and Order ............................................................................................. 9-38
IMMR Bit Descriptions ......................................................................................................... 6-29
EMCR Bit Descriptions ......................................................................................................... 6-30
SYPCR Bit Descriptions........................................................................................................ 6-38
SWSR Bit Descriptions ......................................................................................................... 6-39
TESR Bit Descriptions........................................................................................................... 6-39
TBSCR Bit Descriptions........................................................................................................ 6-42
RTCSC Bit Descriptions........................................................................................................ 6-43
PISCR Bit Descriptions ......................................................................................................... 6-44
PITC Bit Descriptions............................................................................................................ 6-45
PIT Bit Descriptions .............................................................................................................. 6-45
SGPIODT1 Bit Descriptions ................................................................................................. 6-46
SGPIODT2 Bit Descriptions ................................................................................................. 6-47
SGPIOCR Bit Descriptions ................................................................................................... 6-48
Power Mode Control Bit Settings .......................................................................................... 8-17
Power Mode Descriptions...................................................................................................... 8-17
Power Mode Wake-Up Operation ......................................................................................... 8-18
PLPRCR Bit Descriptions ..................................................................................................... 8-34
COLIR Bit Descriptions ........................................................................................................ 8-36
VSRMCR Bit Descriptions.................................................................................................... 8-37
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
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