MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1319
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Part Number:
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Manufacturer:
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Quantity:
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There are two power-up/down options. Choosing which one is required for an application will depend
upon circuitry connected to 2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Power-up/down
option A is required if 2.6-V compliant pins and dual 2.6-V/5-V compliant pins are connected to the 5-V
supply with a pull-up resistor or driven by 5-V logic during power-up/down. In applications for which this
scenario is not true the power-up/down option B may be implemented. Option B is less stringent and easier
to ensure over a variety of applications.
Refer to
The power consumption during power-up/down sequencing will stay below the operating power
consumption specifications when following these guidelines.
G.9.1
The Option A power-up sequence (excluding V
The first step in the sequence is required is due to gate-to-drain stress limits for transistors in the pads of
2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Damage can occur if gate-to-drain voltage
potential is greater than 3.1 V. This is only a concern at power-up/down. The second step in the sequence
is required is due to ESD diodes in the pad logic for dual 2.6-V/5-V compliant pins and 2.6-V pins. The
diodes are forward biased when V
Figure G-1
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same instant or before both the high voltage and low voltage supplies are powered-up.
Freescale Semiconductor
1. V
2. V
Table 2-1
DDH
DDH
illustrates the power-up sequence if no keep-alive supply is required.
Power-Up/Down Option A
≤
≥
The V
rate less that 25V/ms.
V
V
DDL
DDL
Figure G-1. Option A Power-Up Sequence Without Keep-Alive Supply
for a list of 2.6 V and dual 2.6V/5 V compliant pins.
DDH
+ 3.1 V (V
- 0.5 V (V
V
V
DDH
DDH
ramp voltage should be kept below 50V/ms and the V
cannot lead V
cannot lag V
DDH
MPC561/MPC563 Reference Manual, Rev. 1.2
DDH
DDL
cannot lag V
cannot lead V
DDL
is greater than V
DDL
by more than 0.5 V
by more than 3.1 V
3.1-V lead
DDKA
DDL
DDL
NOTE:
0.5-V lag
) is
by more than 0.5 V)
DDH
by more than 3.1 V)
and will start to conduct current.
66-MHz Electrical Characteristics
DDL
Figure G-2
V
V
DDH
DDL
ramp
illustrates the
G-13
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