MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 235

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x2F C00E
0x2F C01C
0x2F C02C
0x2F C03C
0x2F C04C
0x2F C000
0x2F C004
0x2F C008
0x2F C010
0x2F C014
0x2F C018
0x2F C020
0x2F C024
0x2F C028
0x2F C030
0x2F C038
0x2F C040
0x2F C044
0x2F C048
0x2F C050
0x2F C054
Address
1
USIU Module Configuration Register (SIUMCR)
See
System Protection Control Register (SYPCR)
See
Reserved
Software Service Register (SWSR)
See
Interrupt Pending Register (SIPEND).
Interrupt Mask Register (SIMASK)
See
Interrupt Edge Level Mask (SIEL)
See
See
Transfer Error Status Register (TESR)
See
USIU General-Purpose I/O Data Register (SGPIODT1)
See
USIU General-Purpose I/O Data Register 2 (SGPIODT2)
See
See
External Master Mode Control Register (EMCR)
See
Pads Module Configuration Register 2 (PDMCR2)
See
Pads Module Configuration Register (PDMCR)
See
Interrupt Pend2 Register (SIPEND2)
See
Interrupt Pend3 Register (SIPEND3)
See
Interrupt Mask2 Register (SIMASK2)
See
See
Interrupt In-Service2 Register (SISR2)
See
Interrupt In-Service3 Register (SISR3)
See
Interrupt Vector (SIVEC)
USIU General-Purpose I/O Control Register (SGPIOCR)
Interrupt Mask3 Register (SIMASK3)
Table 6-7
Table 6-15
Table 6-16
Section 6.2.2.2.4, “SIU Interrupt Mask Register
Section 6.2.2.2.7, “SIU Interrupt Edge Level Register
Section 6.2.2.2.8, “SIU Interrupt Vector Register
Table 6-17
Table 6-23
Table 6-24
Table 6-25
Table 6-13
Table 2-6
Table 2-5
Section 6.2.2.2.2, “SIU Interrupt Pending Register 2
Section 6.2.2.2.3, “SIU Interrupt Pending Register 3
Section 6.2.2.2.5, “SIU Interrupt Mask Register 2
Section 6.2.2.2.6, “SIU Interrupt Mask Register 3
Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and
Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and
MPC561/MPC563 Reference Manual, Rev. 1.2
for bit descriptions.
for bit descriptions.
for bit descriptions.
Table 5-1. USIU Address Map
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
Unified System Interface Unit (USIU) Overview
(SIMASK),” for bit descriptions.
(SIVEC),” for bit descriptions.
(SIMASK2),” for details.
(SIMASK3),” for details.
(SIPEND2),” for bit descriptions.
(SIPEND3),” for bit descriptions.
(SIEL),” for bit descriptions.
SISR3),” for details.
SISR3),” for details.
5-3