MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 445

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Storage reservation will be cleared regardless of the data phase termination status of the write requests by
another master to the reserved address if the address phase of the write access is terminated normally on
the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx instruction, the
reservation is not guaranteed.
11.6.3
Once the RPCU core reserves a memory location, the L2U module is responsible for snooping the L-bus
and U-bus for possible intrusion of the reserved location. Under certain circumstances, the L2U depends
on the USIU or the UIMB to provide status of reservation on external bus and the IMB3 respectively.
Table 11-2
11.7
The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles
that reflect activity on the L-bus that would otherwise not be visible to the external bus. L-bus show cycles
are software controlled.
Freescale Semiconductor
1
2
3
If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write access
from completing. In this case, the L2U will drive cancel-reservation signal back to the core as soon as it
comes to know that the alternate master on the U-bus has touched the reserved location.
If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it
communicates to the core that the current write has been aborted by the slave with no side effects.
If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request on the
U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination signals and it
communicates to the core if the current write has been aborted by the slave with no side effects.
L-Bus Show Cycle Support
Reserved Location On
lists all reservation protocol cases supported by the L2U snooping logic.
Reserved Location (Bus) and Possible Actions
External Bus
U-bus
L-bus
IMB3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-2. Reservation Snoop Support
Intruding Alternate Master
IMB3-master
Ext-master
U-master
U-master
U-master
U-master
L-master
L-master
L-master
L-master
Request to cancel the reservation.
Request to cancel the reservation.
Block stwcx
Block stwcx
Block stwcx
Block stwcx
Transfer Status
Block stwcx
Block stwcx
Transfer Status
Action Taken on stwcx cycle
2
3
L-Bus to U-Bus Interface (L2U)
1
11-9