MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 382

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
9.5.10
Reservation occurs when a master loads data from memory. The memory location must not be overwritten
until the master finishes processing the data and writing the results back to the reserved location. The
MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus,
storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that an MPC500 processor is notified of
storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to
that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids
the need to have very fast storage reservation loss indication signals routed from every remote bus to every
MPC500 master.
The storage reservation protocol makes the following assumptions:
The reservation protocol for a single-level (local) bus is illustrated in
that an external logic on the bus carries out the following functions:
9-42
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Each processor has, at most, one reservation flag
lwarx sets the reservation flag
lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag
stwcx by the same processor clears the reservation flag
Store by the same processor does not clear the reservation flag
Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag
In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
Snoops accesses to all local bus slaves
Holds one reservation for each local master capable of storage reservations
Sets the reservation when that master issues a load and reserve request
Clears the reservation when some other master issues a store to the reservation address
Storage Reservation
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
9-30. The protocol assumes
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